1. Field of the Invention
The present invention relates to macro cells used for gate arrays, ECAs (embedded cell arrays), and the like.
2. Description of the Prior Art
FIG. 8 is a schematic plan view showing a structure of a conventional semiconductor integrated circuit gate array. Referring to FIG. 8, a semiconductor substrate 101 has a cell area 102 having transistors arranged over all of its surface and forming circuits performing desired functions through connections between the transistors, and a buffer area 103 in which I/O buffers are disposed. The cell area 102 is located at the central portion of the semiconductor substrate 101 and the buffer area 103 is located at the peripheral portion of the semiconductor substrate 101.
In the cell area 102, a macro cell 104 includes logic circuits, such as AND circuits and OR circuits, or circuits having functions on a logic gate level, such as flip-flop circuits, incorporating a plurality of transistors. A macro cell area 105 includes a plurality of macro cells 104 arranged along a row direction, and inter-cell wiring 106 provides connections between macro cells 104 disposed in different macro cell areas 105. A wiring area 107 provides connections between macro cells 104 disposed in different macro cell areas 105 by the inter-cell wiring 106. The macro cell area 105 and the wiring area 107 are alternatingly arranged along a column direction. In FIG. 8, only portions of the macro cell areas 105 and wiring areas 107 are shown.
FIG. 9 is a plan view showing a structure of a conventional macro cell, an enlarged view of the area surrounded by the rectangle 108 of FIG. 8. FIG. 9 shows an example of a four-input NAND circuit shown in FIG. 10. Referring to FIG. 9, a gate electrode 109 is oriented in the column direction (in the Y direction in FIG. 9) and has a first end having a rectangular shape and located at the upper end, a second end having a rectangular shape and located at the lower end, and an effective width portion along a straight line connecting the first end with the second end. A source-drain area 110 is disposed between the effective width portions of adjoining gate electrodes 109. A group of transistors 111, including a plurality of gate electrodes 109 arranged in the row direction (in the X direction in FIG. 9) and having respective source-drain areas 110, is disposed between the effective width portions of adjoining gate electrodes 109. An intra-cell wiring 112 provides a connection between transistors within the macro cell 104. A first contact 113 connects the intra-cell wiring 112 with the source-drain area 110. A second contact 114 connects the intra-cell wiring 112 with the gate electrode 109, and a third contact 115 connects the intra-cell wiring 112 to the inter-cell wiring 106. There are two groups of transistors 111 arranged along the column direction with the positions of the gate electrodes 109 and the positions of the source-drain areas 110 in alignment. The upper group of transistors are P-channel transistors and the lower group of transistors are N-channel transistors. A, B, C, D, and Y in FIG. 9 correspond to A, B, C, D, and Y in FIG. 10, respectively.
The inter-cell wiring 106 lies along the row direction and the column direction. The inter-cell wiring 106 across the macro cell area 105 is aluminum wiring in a second layer (hereinafter called second-layer aluminum wiring) and the rest of the inter-cell wiring 106 is either aluminum wiring in a first layer (hereinafter called first-layer aluminum wiring) or the second-layer aluminum wiring. Meanwhile, the intra-cell wiring 112 lies along the row direction or the column direction and is first-layer aluminum wiring.
Generally, the first-layer aluminum wiring and the second-layer aluminum wiring along the column direction are arranged at a constant wiring pitch along the row direction. The wiring pitch of the first-layer aluminum wiring along the row direction and the wiring pitch of the second-layer aluminum wiring along the row direction are the same. Further, the wiring pitch of the first-layer aluminum wiring and the second-layer aluminum wiring along the row direction is larger than the minimum wiring pitch of the first-layer aluminum wiring and the second-layer aluminum wiring along the row direction that can be achieved due to the limits of the processing technology used to produce the wiring. More specifically, as shown in FIG. 11A, the wiring pitch A of the first-layer aluminum wiring and the second-layer aluminum wiring along the row direction is A=B.times.2+C+D, where B is the minimum distance between the effective width portion of the gate electrode 109 and the first contact 113, C is the length of the effective width portion of the gate electrode 109 along the row direction, and D is the length of the first contact 113 along the row direction. As shown in FIG. 11B, the minimum wiring pitch E of the first-layer aluminum wiring and the second-layer aluminum wiring along the row direction achievable considering the limits of the processing technology used is E=F+G, where F is the length of the first-layer aluminum wiring and the second-layer aluminum wiring along the row direction, G is the wiring distance between the first-layer aluminum wiring and the second-layer aluminum wiring, and A&gt;E.